Efficient high-speed/low-power pipelined architecture for the direct 2-D discrete wavelet transform

In this paper, we present our proposed architecture (PA) for the direct two -dimensional discrete wavelet transform (DWT), which performs a complete dy adic (i.e., nonstandard) decomposition of an N-0 x N-0 image in approximate ly N-0(2)/4 clock cycles (ccs), Therefore, it consistently speeds up the pe rformance? of other known architectures, which commonly need approximately N-0(2) ccs. Also, if has an AT(2) complexity, which is notably lon er than that of other devices based on the "direct approach." This result has been achieved by means of carefully balanced pipelining and has two "faces," First, PA can be employed for performing processing: four times faster than allowed by other architectures working at the same clock frequency (high-speed utilization). Second, it can be employed even using a four times lower clock frequency but reaching the same performance as oth er architectures. This second possibility allows of reducing the supply vol tage and the power dissipation respectively by four and by 16 with respect to other architectures (low-power utilization).