A high-speed residue-to-binary converter for three-moduli (2(k), 2(k)-1, 2(k-1)-1) RNS and a scheme for its VLSI implementation

In this paper, a high-speed residue-to-binary converter for the moduli set (2(k), 2(k) - i, 2(k-1) - 1) is proposed. Compared to the previous converte r based on this moduli set, the proposed one is 40% faster. Also, the time- complexity product is improved by 20%. Following the top-down very large sc ale integration design flow, the proposed converter is implemented in 0.5-m icron CMOS technology. Based on this moduli set, layouts of the 8-, 16-, 32 - and 64-bit residue-to-binary converters, which can be used in further res idual number sg stem designs, are generated and simulation results obtained .