Embedded processor core with 64-bit architecture and its system-on-chip integration for digital consumer products

A 64-bit architecture for an embedded processor targeted for next-generatio n digital consumer products has been developed. It has dual-mode instructio n sets and is optimized for high multimedia performance, provided by SIMD/f loating-point vector instructions in 32-bit length LSA, and small code size , provided by a conventional 16-bit length ISA. Large register files, (64 x 64b and 64 x 32b), a split-branch mechanism, and virtual cache are also ad apted in the architecture. A 714MIPS/9.6 GOPS/400MHz processor core with th e 64-bit architecture and a system LSI containing the core are developed us ing 0.15-mum technology. The LSI includes a 3.2 GB/sec high-bandwidth on-ch ip bus, a high-speed DRAM interface, a SRAM/Flash/ROM/Multiplexed-bus inter face, and a 66 MHz PCI interface that provide the performance required for next-generation multimedia applications.