A low power media processor core performable CIF30 fr/s MPEG4/H26x video codec

An architectural design of a media processor core optimized for MPEG4/H26x video codec targeted for use in mobile multimedia terminals [1] is presente d. The architecture consists of a maximum 6.4 GOPS SIMD (Single Instruction Multiple Data) processor, RISC-processor, VLC-processor, and intelligent D MA controller. The unique SIMD processor completes 2-D DCT processing in 13 2 clock cycles, or block matching (16 by 16 pixels) in 24 clock-cycles. VLC -processor allows the completion of 8 by 8 block run-level coding in averag e 10 clock cycles in the case of low bit-rates. The functions of transpose- registers in the SIMD processor, data sub-sampling technique in the DMA, or data-sliding technique between PEs (Processor Elements) in the SIMD proces sor eliminate a large amount of cycle loss for data handling, and extract t he highest level of performance. Through the use of the above architecture and the lower power approach, CIF 30 frames/s MPEG4 Simple Profile video co dec @ 100 MHz can be achieved. Estimated dissipation is as low as 280 mW. 3 00 kgates and 16 kBytes four port SRAM are contained on a 12 mm(2) area by using 0.18 mum process technology. The combination of the RISC-processor an d SIMD-processor can also operate MPEG4 core profile (shape coding) that re quires flexibility and performance.