Fully digital preambleless 40 Mbps QPSK receiver for burst transmission

We present a case of design and implementation of a high-speed burst QPSK ( Quaternary Phase Shift Keying) receiver. Since the PSK modulation carries i ts information through the phase, the baseband digital receiver can recover transmitted symbol from the received phase. The implemented receiver estim ates symbol time and frequency offset using sampled data over 32 symbols wi thout transmitted symbol information, and embedded RAM is used for received phase delay over estimation time. The receiver is implemented using about 92,000 gates of Samsung KG75 SOG library which uses 0.65 mum CMOS technolog y. The fabricated chip test result shows that the receiver operates at 40 M Hz clock rate on 5.6 V, which is equivalent to the 40 Mbps data rate.