A high-performance videophone chip with dual multimedia VLIW processor cores

A chip is described that integrates two multimedia VLIW processor cores wit h a hardware streaming engine [1]. It can implement a real-time videophone, or an MPEG4 codec. Each processor core has identical resources, and shares the memory and system I/O interface units. With its symmetric structure. a pplications can be executed on either processor without constraints. To acc elerate multimedia-specific applications, the architecture of this processo r has several features. It merges the features of a RISC and a DSP, its ins truction set is extended to accelerate both Video and audio applications, a nd it supports an efficient embedded memory system, to reduce both the band width and the latency for multimedia applications needing frequent memory a ccesses. The chip size will be 100mm(2) die that contains 700 K logic gates , 60 KB RAM, and 16 KB ROM in a 0.25-mum CMOS standard cell technology. At 65 MHz operating frequency, it can process H.263 Video coding at CIF 15 fra mes/sec, and G.723.1 audio coding with an 80% processing time allocation.