A low-power high-performance vector-pipeline DSP for low-rate videophones

We propose a vector-pipeline processor VP-DSP for low-rate videophones whic h can encode and decode 10 frames/sec, of QCIF through a 29.2 kbps low-rate line. We have already fabricated a VP-DSP LSI by a 0.35 mum CMOS process. The area of the VP-DSP core is 4.26 mm(2). It works properly at 25 MHz/1.6 V with a power consumption of 49 mW. Its peak performance is up to 400 MOPS , 8.2 GOPS/W.