An embedded software scheme for a real-time single-chip MPEG-2 encoder system with a VLIW media processor core

Citation
H. Segawa et al., An embedded software scheme for a real-time single-chip MPEG-2 encoder system with a VLIW media processor core, IEICE TR EL, E84C(2), 2001, pp. 202-211
Citations number
15
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEICE TRANSACTIONS ON ELECTRONICS
ISSN journal
09168524 → ACNP
Volume
E84C
Issue
2
Year of publication
2001
Pages
202 - 211
Database
ISI
SICI code
0916-8524(200102)E84C:2<202:AESSFA>2.0.ZU;2-D
Abstract
This paper describes an embedded software scheme for a single-chip MPEG-2 e ncoder that executes concurrent video, audio, and system encoding in real-t ime. The software features a scalable module structure, which is hierarchic ally composed and has expandable plug-in modules. For increased applicabili ty, several task-modules are prepared for the respective video. audio, and system processing. In addition, an effective task management scheme that fe atures polling and interrupt-based task switching has been proposed in orde r to achieve real-time operation. The software having these features and in cluding all task-modules is implemented on a single media-processor D30V on a single chip MPEG-2 video, audio, and system encoder. This encoder realiz es real-time MPFG-2 video encoding, Dolby Digital or MPEG-1 audio encoding, and system encoding that generates TS or PS over 50 Mbps for various appli cations. Assuming a DVD or DTV encoder system, the software is reconstructe d with less than 56.6-kbytes of instruction and 145.6 MIPS performance. The single medic-processor with 64-kbytes of instruction RAM and 162 MIPS perf ormance, running at a clock rate of 162 MHz, can successfully accomplish a real-time operation with the proposed embedded software.