A low power approach to floating point adder design for DSP applications

The demand for high performance, low power floating point adder cores has b een on the rise during the recent years particularly for DSP applications. In this paper, we present a new architecture for a low power, IEEE compatib le, floating point adder, that is fast and has low latency. The functional partitioning of the adder into three distinct, clock gated data paths allow s activity reduction. The switching activity function of the proposed adder is represented as a three state FSM. During any given operation cycle, onl y one of the data paths is active, during which time, the logic assertion s tatus of the circuit nodes of the other data paths are held at their previo us states. Critical path delay and latency are reduced by incorporating spe culative rounding and pseudo leading zero anticipatory logic as well as dat a path simplifications. In contrast to conventional high speed floating poi nt adders that use leading zero anticipatory logic, the proposed scheme off ers a worst case power reduction of 50%.