Process and structure designs for high performance Cu low-k interconnects

Integration of low-k dielectrics and Cu-interconnects is a key factor to im prove ULSI devices for 0.1 mum-generation. The difficulty is how to reduce the interconnect capacitance with keeping their mechanical strength and the adhesion strength. These characteristics depend not only on the low-k mate rial itself, but also on the deposition process. Namely, the plasma polymer ization method is superior to the process compatibility in the multilevel i nterconnect formation. The highly thermal-stable, p-BCB polymers with k = 2 .5 similar to 2.6 enabled us to make high-speed CMOS logic-LSIs with multi- level low-k/Cu interconnects.