We have developed a fast programmable trigger processor board based on a fi
eld programmable gate array and a complex programmable logic device for use
in the BELLE experiment. The trigger board accommodates 144 ECL input sign
als, 2 NIM input signals, 24 ECL output signals, and the VME bus specificat
ion. An asynchronous trigger logic for counting isolated clusters is used.
We have obtained a trigger latency of 50 ns with full access to input and o
utput signals via a VME interface. The trigger logic can be modified at any
time depending on the experimental conditions. (C) 2001 Elsevier Science B
.V. All rights reserved.