Sub-100-nm device fabrication using proximity X-ray lithography at five levels

We applied proximity X-ray lithography at five levels (mark, isolation, gat e, contact and wiring) to fabricate devices at a scale of 100 nm and lower. Low-contrast masks and chemically amplified resists were used, and a criti cal dimension (CD) variation (3 sigma) within 10% of the pattern width at a scale of 100 nm was obtained at each layer. The resolution remained good d own to 80 nm isolation gates at a gap of 15 mum. Overlay accuracy (mean+/- 3 sigma) at each layer was within 40 nm, especially at the contact-hole lay er which was below 25 nm. We evaluated the fabricated device performance fo r subthreshold characteristics, hot-carrier reliability and threshold volta ge fluctuations. Good characteristics were obtained for n-channel metal oxi de semiconductor field effect transistor (n-MOSFET) devices that scale into the 100 nm regime. In this paper, we demonstrate the feasibility of X-ray lithography in process for 100-nm-and-lower devices.