Analysis of the gate capacitance measurement technique and its applicationfor the evaluation of hot-carrier degradation in submicrometer MOSFETs

The use of gate-to-drain capacitance (C-gd) measurement as a tool to charac terize hot-carrier-induced charge centers in submicron n- and p-MOSFET's ha s been reviewed and demonstrated. By analyzing the change in C-gd measured at room and cryogenic temperature before and after high gate-to-drain trans verse field (high field) and maximum substrate current (I-bmax) stress, it is concluded that the degradation was found to be mostly due to trapping of majority carriers and generation of interface states. These interface stat es were found to be acceptor states at top half of band gap for n-MOSFETs a nd donor states at bottom half of band gap for p-MOSFETs. In general, hot e lectrons are more likely to be trapped in gate oxide as compared to hot hol es while the presence of hot holes generates more interface states. Also, w e have demonstrated a new method for extracting the spatial distribution of oxide trapped charge, Q(ot), through gate-to-substrate capacitance (C-gb) measurement. This method is simple to implement and does not require additi onal information from simulation or detailed knowledge of the device's stru cture. (C) 2001 Elsevier Science Ltd. All rights reserved.