2.7V 50MHz IF sampling Delta Sigma modulator with+37dBV IIP3

The design and experimental results of a 2.7V 50MHz switched-capacitor DS m odulator in 0.35 mum BiCMOS process are presented. The circuit is targeted For the IF section of a radio receiver in a GSM cellular phone. It combines Frequency downconversion with analogue to digital conversion by directly s ampling an input signal from an IF of 50MHz. The measured peak signal-to-no ise ratio for a 100kHz bandwidth is 81dB with a 53MHz blocking signal and t he measured IIP3 for IF input is +36.9dBV.