Correlated double sampling integrator insensitive to parasitic capacitance

Authors
Kajita, T Temes, GC Moon, UK
Citation
T. Kajita et al., Correlated double sampling integrator insensitive to parasitic capacitance, ELECTR LETT, 37(3), 2001, pp. 151-153
Citations number
4
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
ELECTRONICS LETTERS
ISSN journal
00135194 → ACNP
Volume
37
Issue
3
Year of publication
2001
Pages
151 - 153
Database
ISI
SICI code
0013-5194(20010201)37:3<151:CDSIIT>2.0.ZU;2-G
Abstract
A nsw correlated double sampling (CDS) scheme is proposed which improves th e operation of an integrator with a large parasitic capacitor at the: input node of an oy-amp. Tt suppresses the effects of the 1/f noise and offset v oltage of the op-amp, as well as the kTC charge noise from the parasitic ca pacitor. It also reduces charge injection and clock feedthrough effects.