Cellular automata-based recursive pseudoexhaustive test pattern generator

This paper presents a recursive technique for generation of pseudoexhaustiv e test patterns. The scheme is optimal in the sense that the first 2(k) vec tors cover all adjacent k-bit spaces exhaustively. It requires substantiall y lesser hardware than the existing methods and utilizes the regular, modul ar, and cascadable structure of local neighborhood Cellular Automata (CA), which is ideally suited for VLSI implementation. In terms of XOR gates, thi s approach outperforms earlier methods by 15 to 50 percent. Moreover, test effectiveness and hardware requirements have been established analytically, rather than by simple simulation and logic minimization.