A model of the stress induced leakage current in gate oxides

Citation
L. Larcher et al., A model of the stress induced leakage current in gate oxides, IEEE DEVICE, 48(2), 2001, pp. 285-288
Citations number
15
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON ELECTRON DEVICES
ISSN journal
00189383 → ACNP
Volume
48
Issue
2
Year of publication
2001
Pages
285 - 288
Database
ISI
SICI code
0018-9383(200102)48:2<285:AMOTSI>2.0.ZU;2-K
Abstract
A new quantitative model of the stress induced leakage current (SILC) in MO S capacitors with thin oxide layers has been developed by assuming the inel astic trap-assisted tunneling as the conduction mechanism. The oxide band s tructure has been simplified by replacing the trapezoidal barrier with two rectangular barriers. An excellent agreement between simulations and experi ments has been found by adopting a trap distribution Gaussian in space and in energy. Only minor variations pf the trap distribution parameters were o bserved by increasing the injected charge during electrical stress, indicat ing that oxide neutral defects with similar characteristics are generated a t any stage of the stress.