Experimental determination of the maximum post-process annealing temperature for standard CMOS wafers

This paper reports on the experimental determination of the maximum post-pr ocess annealing temperature for standard 0.35 mum CMOS wafers with Aluminum based interconnections and tungsten plugs, without introducing significant modifications to their standard characteristics. The impact of increasing the postprocessing temperature from 475 degreesC to 575 degreesC, for perio ds varying between 30 and 90 min, on both the front and back end is analyze d. 0.35 mum CMOS technologies with different Al alloys, Al-1wt%Si-0.5wt%Cu (AlSiCu) or Al-0.5wt%Cu (AlCu), and different back end structures are consi dered. It is illustrated that the maximum annealing temperature is a functi on of the structure and composition of the interconnection layers and their maximum allowable resistance increase. It is also demonstrated that the tr ansistor characteristics, the silicide quality and the leakage currents are as good as unaffected by annealing for 90 min at temperatures up to 525 de greesC.