Single-event upset and snapback in silicon-on-insulator devices and integrated circuits

The characteristics of ion-induced charge collection and single-event upset are studied in silicon-on-insulator (SOI) transistors and circuits with va rious body tie structures. Impact ionization effects, including single-even t snapback, are shown to be very important. Focused ion microbeam experimen ts are used to find single- event snapback drain voltage thresholds in n-ch annel SOI transistors as a function of device width. Three-dimensional devi ce simulations are used to determine single-event upset and snapback thresh olds in SOI SRAMs, and to study design tradeoffs for various body-tie struc tures. A window of vulnerability to single-event snapback is shown to exist below the single event upset threshold. The presence of single-event snapb ack in commercial SOI SRAMs is confirmed through broadbeam ion testing, and implications for hardness assurance testing of SOI integrated circuits are discussed.