Worst-case bias during total dose irradiation of SOI transistors

Authors
Ferlet-Cavrois, V Colladant, T Paillet, P Leray, JL Musseau, O Schwank, JR Shaneyfelt, MR Pelloie, JL de Poncharra, JD
Citation
V. Ferlet-cavrois et al., Worst-case bias during total dose irradiation of SOI transistors, IEEE NUCL S, 47(6), 2000, pp. 2183-2188
Citations number
18
Categorie Soggetti
Apllied Physucs/Condensed Matter/Materiales Science","Nuclear Emgineering
Journal title
IEEE TRANSACTIONS ON NUCLEAR SCIENCE
ISSN journal
00189499 → ACNP
Volume
47
Issue
6
Year of publication
2000
Part
3
Pages
2183 - 2188
Database
ISI
SICI code
0018-9499(200012)47:6<2183:WBDTDI>2.0.ZU;2-8
Abstract
The worst case bias during total dose irradiation of partially depleted SOI transistors from two technologies is correlated to the device architecture . Experiments and simulations are used to analyze SOI back transistor thres hold voltage shift and charge trapping in the buried oxide.