Circuit technique for threshold voltage stabilization using substrate biasin total dose environments

Citation
Jk. Shreedhara et al., Circuit technique for threshold voltage stabilization using substrate biasin total dose environments, IEEE NUCL S, 47(6), 2000, pp. 2557-2560
Citations number
9
Categorie Soggetti
Apllied Physucs/Condensed Matter/Materiales Science","Nuclear Emgineering
Journal title
IEEE TRANSACTIONS ON NUCLEAR SCIENCE
ISSN journal
00189499 → ACNP
Volume
47
Issue
6
Year of publication
2000
Part
3
Pages
2557 - 2560
Database
ISI
SICI code
0018-9499(200012)47:6<2557:CTFTVS>2.0.ZU;2-#
Abstract
Radiation tolerance of CMOS circuits to total dose can be improved by adjus ting the p-substrate voltage to keep the n-channel threshold voltage above a minimum value, This paper presents a circuit design, implemented on an IC and on a breadboard, for dynamically adjusting the substrate voltage. Expe rimental results clearly show that devices with threshold voltage stabiliza tion exhibit longer lifetime a's compared to those without the stabilizatio n circuit.