Clock buffer circuit soft errors in antifuse-based field programmable gatearrays

Three-dimensional mixed-mode device simulation is used to investigate the d ock upset in an antifuse FPGA device. Two versions of the clock circuit wer e simulated, the original and the redesigned,vith improved SEU hardness, Th e threshold LET of each version was simulated both at static and during tra nsition. Compared to the test data, the simulated results consistently unde restimate the LETth. The difference between LETth at static and during tran sition is relatively small. This disagrees with the previous speculation th at the clock upset is due to heavy-ion strikes very close to the clock edge . Efforts were also made to optimize the simulation methodology to reduce t he simulation time for practicality.