Improving path delay testability of sequential circuits

We analyze the causes of low path delay fault coverage in synchronous seque ntial circuits and propose a method to improve testability. The three main reasons fur low path delay fault coverage are found to be: A) combinational ly false (nonactivatable) paths; B) sequentially nonactivatable paths; and C) unobservable fault effects. Accordingly, we classify undetected faults i n Groups A, B, and C, Combinationally false paths can be made testable by m odifying the circuit or resynthesizing the combinational logic as discussed by other researchers. A majority of the untestable faults are, however, fo und in Group B, where a signal transition cannot be functionally propagated through a combinational path. A test requires two successive states necess ary to create a signal transition and propagate it through the target path embedded in the sequential circuit. We study a partial scan technique in wh ich flip-flops are scanned to break cycles and show that a substantial incr ease in the coverage of path delay faults is possible.