Partitioning algorithm to enhance pseudoexhaustive testing of digital VLSIcircuits

This brief introduces a partitioning algorithm, which facilitates pseudoexh austive testing, to detect and locate faults in digital VLSI circuits. The algorithm is based on an analysis of circuit's primary input cones and fano ut (PIFAN) values. An invasive approach is employed, which creates logical and physical partitions by automatically inserting reconfigurable test cell s and multiplexers. The test cells are used to control and observe multiple partitioning points, while the multiplexers expand the controllability and observability provided by the test cells. The feasibility and efficiency o f our algorithm are evaluated by partitioning numerous ISCAS 1985 and 1989 benchmark circuits containing up to 5597 gates. Our results show that the P IFAN algorithm offers significant reductions in overhead and test time when compared to previous partitioning algorithms.