L. Czuni et T. Sziranyi, Motion Segmentation and tracking with edge relaxation and optimization using fully parallel methods in the cellular nonlinear network architecture, REAL-TIME I, 7(1), 2001, pp. 77-95
In this paper we outline a fully parallel and locally connected computation
model for the segmentation of motion events in video sequences based on sp
atial and motion information. Extraction of motion information from video s
eries is very time consuming. Most of the computing effort is devoted to th
e estimation of motion vector fields, defining objects and determining the
exact boundaries of these objects. The split and merge segmentation of diff
erent small areas, those obtained by oversegmentation, needs an optimizatio
n process. In our proposed algorithm the process starts from an oversegment
ed image, then the segments are merged by applying the information coming f
rom the spatial and temporal auxiliary data: motion fields and motion histo
ry, calculated from consecutive image frames. This grouping process is defi
ned through a similarity measure of neighboring segments, which is based on
intensity, speed and the time-depth of motion-history. There is also a fee
dback for checking the merging process, by this feedback we can accept or r
efuse the cancellation of a segment-border. Our parallel approach is indepe
ndent of the number of segments and objects, since instead of graph represe
ntation of these components, image features are defined on the pixel level.
We use simple VLSI implementable functions like arithmetic and logical ope
rators, local memory transfers and convolution. These elementary instructio
ns are used to build up the basic routines such as motion displacement fiel
d detection, disocclusion removal, anisotropic diffusion, grouping by stoch
astic optimization. This relaxation-based motion segmentation can be a basi
c step of the effective coding of image series and other automatic motion t
racking systems. The proposed system is ready to be implemented in a Cellul
ar Nonlinear Network chip-set architecture. (C) 2001 Academic Press.