Evaluating trace cache on moderate-scale processors

Trace cache is a new instruction supply mechanism for wide-issue superscala r processors. It caches dynamic instruction traces, each of which consists of multiple basic blocks. As a result, a number of basic blocks are combine d into a single large unit, and hence the effective fetch bandwidth is enla rged. The trace cache has been evaluated only on much aggressive superscala r processors. However. an efficient instruction supply mechanism is require d also for moderate-scale processors, as media-specific applications increa se their importance. The paper evaluates the trace cache fetch mechanism on moderate-scale superscalar processors. A simpler trace cache is proposed n amed nonconsecutive basic block buffer (NCB), for the processors. From expe rimental evaluation, using the NCB improves the instruction supply efficien cy by approximately 10% and hence processor performance is also improved by approximately 10% for integer programs.