Simultaneous optimisation of dynamic power, area and delay in behavioural synthesis

Concern over power dissipation, coupled with the continuing rise in system size and complexity, means that there is a growing need for high-level desi gn tools capable of doubt automatically optimising systems to take into acc ount power dissipation, in addition to the more conventional metrics of are a, delay and testability. Current methods for reducing power consumption te nd to be ad-hoc: for example, slowing down. or turning off idle parts of th e system, or a controlled reduction in power supply The behavioural synthes is system described here features an integrated incremental power estimatio n capability, which makes use of activity profiles, generated automatically through simulation of a design on any standard VHDL simulator; accurate ci rcuit-level cell models (generated, again automatically, via SPICE simulati on); and a comprehensive system power model. This data, along with similar estimators for. area and delay, guides the optimisation of a design towards independent user-specified objectives for final area, delay, clock speed, and energy consumption. Tn addition, a range of power reducing features are included, encompassing: supply voltage scaling, clock gating, input latchi ng, input gating, low-power cells, and pipelined and multicycle units. Thes e are automatically exploited during optimisation as part of the area/delay /power dissipation trade-off process. The resulting system is capable of re ducing the estimated energy consumption of several benchmark designs by fac tors of between 3.5 and 7.0 times. Furthermore, the design exploration capa bility enables a range of alternative structural implementations to be gene rated from a single behavioural description, with differing art area/dealy/ power trade-offs.