Switching activity estimation under real-gate delay using timed Boolean functions

A probabilistic method to estimate the switching activity of a combinationa l circuit under a real-gate delay model considering temporal, structural an d input pattern dependencies is introduced. It is proved that the switching activity evaluation problem is reduced to the zero-delay problem at specif ic time instances. A mathematical model based on Markov stochastic processe s, which describes the temporal and spatial correlation in terms of the ass ociated zero-delay parameters, is presented. To handle the influence of tim e on glitch generation, the theory of the timed Boolean function (TBF) is a dopted. Additionally, an algorithm to evaluate the switching activity at sp ecific time instances using TBF-ordered binary decision diagrams (TBF-OBDDs ) is given. Comparative study of benchmark circuits demonstrates the accura cy and efficiency of the proposed method.