An asynchronous instruction length decoder

This paper describes an investigation of potential advantages and pitfalls of applying an asynchronous design methodology to an advanced microprocesso r architecture. A prototype complex instruction set length decoding and ste ering unit was implemented using self-timed circuits. [The Revolving Asynch ronous Pentium(R) Processor Instruction Decoder (RAPPID) design implemented the complete Pentium II(R) 32-bit MMX instruction set.] The prototype chip was fabricated on a 0.25-mu CMOS process and tested successfully. Results show significant advantages-in particular, performance of 2.5-4.5 instructi ons per nanosecond-with manageable risks using this design technology, The prototype achieves three times the throughput and half the latency, dissipa ting only half the power and requiring about the same area as the fastest c ommercial 400-MHz clocked circuit fabricated on the same process.