A one-wire approach for skew-compensating clock distribution based on bidirectional techniques

A clock-deskew buffer using the delay-locked loop and the bidirectional tec hnique has been developed. It needs only one wire to synchronize the clocks for a chip-to-chip system, It has been fabricated by a 0.35-mum n-well CMO S process. Experimental results demonstrate that it can achieve the peak-to -peak jitter smaller than 100 ps through a two-meter coaxial cable while op erating at the frequency of 120 MHz. The total power dissipation of the ske w buffer is 218 mW for a 3-V supply, The core chip area is 980 x 1700 mum(2 ).