The twin-transistor noise-tolerant dynamic circuit technique

This paper describes a new circuit technique for designing noise-tolerant d ynamic logic. It is shown that voltage scaling aggravates the crosstalk noi se problem and reduces circuit noise immunity, motivating the need for nois e-tolerant circuit design. In a 0.35-mum CMOS technology and at a given sup ply voltage, the proposed technique provides an improvement in noise immuni ty of 1.8 x (for an END gate) and 2.5 x (for an adder carry chain) over dom ino at the same speed. A multiply-accumulate circuit has been designed and fabricated using a 0.35-mum process to verify this technique. Experimental results indicate that the proposed technique provides a significant improve ment in the noise immunity of dynamic circuits (>2.4x) with only a modest i ncrease in power dissipation (15%) and no loss in throughput.