A 15-b pipelined CMOS floating-point A/D converter

A floating-point approach can be used to extend the dynamic range of analog to-digital (A/D) converters in applications where large signals need not b e encoded with a precision greater than that required for small signals. Ow ing to the nonuniform nature of the quantization in a floating-point A/D co nverter (FADC), it is possible to sacrifice a large peak signal-to-noise ra tio to obtain savings in power dissipation and area while achieving a large dynamic range, A 15-b switched-capacitor pipelined FADC has been designed with a 10-b mant issa and an exponent that provides an additional 5 bits of dynamic range, T he increased dynamic range is obtained with a three-stage pipelined variabl e gain amplifier, while the mantissa is determined by a uniform 10-b pipeli ned A/D converter. An experimental prototype of the converter has been inte grated in a 0.5-mum CMOS technology. It achieves a dynamic range of 90 dB a t a conversion rate of 20 MSamples/s with a total power dissipation of 380 mW.