To make three-dimensional (3-D) on-chip interconnect inductance extraction
tractable, it is necessary to ignore parasitic couplings without compromisi
ng critical properties of the interconnect system. It is demonstrated that
simply discarding faraway mutual inductance couplings can lead to an unstab
le approximate inductance matrix. In this paper, we describe an equipotenti
al shell methodology, which generates a partial inductance matrix that is s
parse yet stable and symmetric. We prove the positive definiteness of the r
esulting approximate inductance matrix when the equipotential shells are pr
operly defined. Importantly, the equipotential shell approach also provably
preserves the inductance of loops if they are enclosed entirely within the
shells of their segments. Methods for sizing the shells to control the acc
uracy are presented. To demonstrate the overall efficacy for on-chip extrac
tion, ellipsoid shells, which are a special case of the general equipotenti
al shell approach, are presented and demonstrated for both on-chip and syst
em-level extraction examples.