Interconnect synthesis without wire tapering

Interconnect synthesis techniques, such as wire sizing and buffer insertion /sizing, have proven to be critical for reducing interconnect delays in dee p submicron design. Consequently, the past few years have seen several work s that study buffer insertion, wire sizing, and their simultaneous optimiza tion. For long interconnect, wire tapering, i.e., reducing the wire width a s the distance from the driver increases, can yield better solutions than u niform wire sizing. However, despite its obvious benefits, tapering is not widely used in practice since it is difficult to integrate into a coherent routing methodology, This paper studies the benefits of wire sizing with ta pering when combined with buffer insertion. We first present a theoretical result that shows wire tapering is at most 3.5 % faster than uniform wire s izing when maximal buffer insertion is applied. We then present detailed ex periments that support this result. Consequently, we conclude that it is ge nerally not worthwhile to perform tapering for signal nets. Finally, we pre sent a general formulation and optimal polynomial time algorithm for simult aneous wire sizing and buffer insertion that forbids wire tapering, but inc orporates layer assignment and wire spacing.