On the detectability of CMOS floating gate transistor faults

This paper focuses on the detectability of defects causing the gates of tra nsistors in CMOS integrated circuits to float (open), i.e., on floating gat e transistor (FGT) faults. Such faults are known to occur in practice. It i s increasingly important to consider their detection to meet high quality r equirements for circuits fabricated in deep submicrometer technologies. We focus on the detectability of FGT faults by the standard voltage- and curre nt-based production test strategies that we refer to as static voltage (SV) , dynamic voltage (DV), and static current (SC) test strategies. We demonst rate how the behavior of the devices caused by FGT faults depends on two cl asses of technological and topological parameters: the predictable and unpr edictable parameters. We show that an FGT fault can induce abnormal logic v alues, additional delays, or increased power supply current. We introduce t he concept of a detectability interval, i.e., the range of values an unpred ictable parameter may assume that allows for the fault detection using a sp ecific test strategy. We illustrate how the detectability intervals for the SV and DV strategies complement that of the SC strategy. In addition, a ne w test scheme that results in an increased SC detectability of FGT faults i s developed. Finally, we demonstrate the effects of initial trapped charges and the effects of coupling to surrounding metal on the detectability inte rvals of each of the test strategies.