A timing-driven pseudoexhaustive testing for VLSI circuits

Because of its ability to detect all nonredundant combinational faults, exh austive testing, which applies all possible input combinations to a circuit , is an attractive test method. However, the test application time for exha ustive testing can he very large. To reduce the test time, pseudoexhaustive testing inserts some bypass storage cells (bscs) so that the dependency of each node is within some predetermined value. Though bsc insertion ran red uce the test time, it may increase circuit delay. In this paper, our object ive is to reduce the delay penalty of bsc insertion for pseudoexhaustive te sting. We first propose a tight delay lower bound algorithm, which estimate s the minimum circuit delay for each node after hse insertion. By understan ding how the lower bound algorithm loses optimality, we can propose a bsc i nsertion heuristic that tries to insert bscs so that the final delay is as close to the lower hound as possible. Our experiments show that the results of our heuristic are either optimal because they are the same as the delay lower bounds or they are very close to the optimal solutions.