Converter-free multiple-voltage scaling techniques for low-power CMOS digital design

Recent research has shown that voltage scaling is a very effective techniqu e for low-power design. This paper describes a voltage scaling technique to minimize the power consumption of a combinational circuit. First, the conv erter-free multiple-voltage (CFMV) structures are proposed, including the p -type, the n-type, and the two-way CFMV structures. The CFMV structures mak e use of multiple supply voltages and do not require level converters. In c ontrast, previous works employing multiple supply voltages need level conve rters to prevent static currents, which may result in large power consumpti on. In addition, the CFMV structures group the gates with the same supply v oltage in a cluster to reduce the complexity of placement and routing for t he subsequent physical layout stage. Next, we formulated the problem and pr oposed an efficient heuristic algorithm to solve it. The heuristic algorith m has been implemented in C and experiments were performed on the ISCAS85 c ircuits to demonstrate the effectiveness of our approach.