Reducing voltage sags through fault current limitation

Citation
F. Tosato et S. Quaia, Reducing voltage sags through fault current limitation, IEEE POW D, 16(1), 2001, pp. 12-17
Citations number
9
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON POWER DELIVERY
ISSN journal
08858977 → ACNP
Volume
16
Issue
1
Year of publication
2001
Pages
12 - 17
Database
ISI
SICI code
0885-8977(200101)16:1<12:RVSTFC>2.0.ZU;2-C
Abstract
Short circuit current limitation in distribution utilities can be an effect ive way to improve power quality, since the expected voltage sag amplitude during faults can be dramatically reduced. A simple series LC circuit tuned at the net frequency, with the capacitor s hunted by a metal oxide varistor (MOV), proves to be a well suited limiter to reach the goal. In the paper, the properties of such a circuit are analy zed and its operation is investigated through computer simulation. The rele vant pro and con aspects are outlined and discussed.