Combinatorial fabrication process for a-Si : H thin film transistors

A combinatorial approach is proposed and demonstrated for the parallel fabr ication of a-Si:H, alloy and a-Si:H based devices, by employing simple mask ing schemes in conventional plasma-enhanced chemical vapor deposition (PECV D). The results are presented for a-Si:H thin film transistors. A (7 x 7) c ombinatorial device library was deposited on a (indium tin oxide/glass) sub strate with the thicknesses of a-SiN:H and a-Si:H as combinatorial variable s along the X and Y axes, respectively. Different a-Si:H TFTs in the librar y were evaluated to yield electrical performance with on-to-off current rat ios exceeding 10(4) and threshold voltages from 0.3 to 4.5 V. Combinatorial PECVD offers an efficient and low cost means of studying the a-Si:H device performance and optimization.