Solder joint reliability of wafer level chip scale packages (WLCSP): A time-temperature-dependent creep analysis

Citation
Jh. Lau et al., Solder joint reliability of wafer level chip scale packages (WLCSP): A time-temperature-dependent creep analysis, J ELEC PACK, 122(4), 2000, pp. 311-316
Citations number
19
Categorie Soggetti
Mechanical Engineering
Journal title
JOURNAL OF ELECTRONIC PACKAGING
ISSN journal
10437398 → ACNP
Volume
122
Issue
4
Year of publication
2000
Pages
311 - 316
Database
ISI
SICI code
1043-7398(200012)122:4<311:SJROWL>2.0.ZU;2-N
Abstract
A novel and reliable wafer level chip scale package (WLCSP) is investigated in this paper. It consists of a copper conductor layer and two low cost di electric layers. The bump geometry consists of the eutectic solder, the cop per core, and the under bump metallurgy. Nonlinear time-temperature-depende nt finite element analyses are performed to determine the shear stress, she ar creep strain, shear stress and shear creep strain hysteresis loops, and creep strain energy density of the corner solder joint. The thermal-fatigue life of the corner solder joint is then predicted by the averaged creep st rain energy density range per cycle and a linear fatigue crack growth rate theory. The WLCSP solder bumps are also subjected to shear test. Finally, t he WLCSP solder joints are subjected to both mechanical shear and thermal c ycling tests.