MODELING TESTING-STRATEGIES FOR YIELD ENHANCEMENT OF MULTICHIP-MODULESYSTEMS

This paper presents analytic models for evaluating test-strategy (TS) for yield enhancement of systems manufactured using fault-tolerant (FT ol) multichip modules (MCM) for massively parallel computing. Several methods for testing FTol-MCM have been proposed, but there is little a nalytic evaluation. This paper uses a novel Markov model to compute th e yield. Unlike a previous method which uses a binomial distribution, our TS can use intermediate tests (Intmed-T). This paper shows an effi cient TS with a modest level of redundancy to achieve 100% first-pass MCM yield for a particular system. Two methods using Intmed-T for FTol -MCM are proposed & analyzed. When Intmed-T are used for all mounted c hips, FTol-MCM with more than a few chips require known-good chips of at least a 99.9% probability-good for achieving a high yield. An effic ient TS with a modest level of redundancy can exist for achieving a 10 0% first-pass MCM yield for a particular system. A yield-analysis mode l using the Least Recently Tested (LRT) TS in this paper provides a ve ry good figure-of-merit due to its cost, delivery, number of tests, an d reliability benefits for current technology. Extensive parametric re sults for the analysis show that LRT-TS can be applied to calculate th e overall yield for FTol-MCM more accurately & efficiently, thereby im proving the system reliability.