Fully integrated standard cell digital PLL

A fully integrated digital phase-locked loop (PLL) used as a clock multiply ing circuit is designed. The PLL is made from standard cells found in almos t any commercial standard cell library and therefore portable between proce sses in netlist format. Using a 0.35 mum standard complementary metal-oxide -semicondctor CMOS process and a 3.0V supply voltage, the PLL is designed f or a locking range of 170 to 360MHz and occupies an on-chip area of 0.06mm( 2).