Multilayer planarization of polymer dielectrics

Polymers are widely used in the microelectronics industry as thin-film inte rlevel dielectrics layers between metal lines, as passivation layers on sem iconductor devices and in various packaging applications, As multiple layer s of polymer and patterned metal are constructed, the ability of these poly mers to planarize topographical features becomes increasingly important. In this study, the degree of planarization (DOP) for five commercially availa ble polymers has been examined for three different structural configuration s with the intent of simulating practical applications. Specifically, this study investigates single layer planarization, multiple coat planarization, and planarization of metal lines patterned on a polymer base. This study a lso examines the effects of orientation of the metal structure to polymer f low during spin casting and location on the wafer. The polymers were select ed to investigate different polymer chemistries frequently used in the micr oelectronics industry. The underlying structures were fabricated using stan dard photolithography and electroplating techniques. Feature dimensions inc lude 25-200 mum line spacings and widths with the polymer overcoat thicknes s being twice the height of the underlying structures.