Pipeline vectorization

This paper presents pipeline vectorization, a method for synthesizing hardw are pipelines based on software vectorizing compilers. The method improves efficiency and ease of development of hardware designs, particularly for us ers with little electronics design experience. We propose several loop tran sformations to customize pipelines to meet hardware resource constraints wh ile maximizing available parallelism. For runtime reconfigurable systems, w e apply hardware specialization to increase circuit utilization. Our approa ch is especially effective for highly repetitive computations in digital si gnal processor (DSP) and:multimedia applications. Case studies using field programmable gate arrays (FPGAs)-based platforms are presented to demonstra te the benefits of our approach and to evaluate tradeoffs between alternati ve implementations. For instance, the loop-tiling transformation, has been found to improve vectorization performance 30-40 times above a PC-based sof tware implementation, depending on whether runtime reconfiguration (RTR) is used.