A bipartition-codec architecture to reduce power in pipelined circuits

This paper proposes a new approach to synthesize pipelined circuits with lo w-power consideration. We treat each output value of a combinational circui t as one state of a finite-state machine (FSM), If the output of a combinat ional circuit transits mainly among some few states, we could extract those states (output) and the corresponding input to build a subcircuit. After b ipartitioning the circuit, we apply the encoding technique to the highly ac tive subcircuit for further power reduction. In this paper, we formulate th e bipartition problem and present a probabilistic-driven algorithm to bipar tition a circuit so as to minimize the power dissipation. Our experimental results show that an average power reduction on several Microelectronic Cen ter of North Carolina (MCNC) benchmarks of 31.6% is achievable.