This paper presents a new tool for the synthesis of low-power VLSI designs,
specifically, those designs targeting digital signal processing applicatio
ns. The synthesis tool genetic algorithm for low-power synthesis (GALOPS) u
ses a genetic algorithm to apply power-reducing transformations to high-lev
el signal-processing designs, producing designs that satisfy power requirem
ents as well as timing and area constraints. GALOPS uses problem-specific g
enetic operators that are specifically tailored to incorporate VLSI-based d
igital signal processing design knowledge. A number of signal-processing be
nchmarks are used to facilitate the analysis of low-power design tools, and
to aid in the comparison of results. Results demonstrate that GALOPS achie
ves significant power reductions in the presented benchmark designs. In add
ition, GALOPS produces a family of unique solutions for each design, all of
which satisfy the multiple design objectives, providing flexibility to the
VLSI designer.