Integrity of ultrathin gate oxides with different oxide thickness, substrate wafers and metallic contaminations

The integrity of ultrathin gate oxides was investigated as a function of po lished and epitaxial wafer surfaces with various gettering sites. After int entional contamination of wafers with 1 x 10(11) atoms/cm(2) and 5 x 10(12) atoms/cm(2) Cu and Ni by a spin-on technique of high reproducibility, we p erformed 0.18-mum low-thermal-budget CMOS process runs. Thermal oxides were grown with various gate oxides in the range of 5-17 nm. After a MOS-capaci tor fabrication we applied a ramped current-density test to study the gate- oxide integrity. Generally, thinner gate oxides exhibited a much more robus t behavior than thicker oxides. The gate-oxide integrity was strongly influ enced by different gettering sites. Although a higher Ni contamination led to a higher number of gate-oxide failures. Cu contamination exhibited a hig her impact on the gate-oxide integrity than Ni.