A CMOS ADSL codec for central office applications

A CMOS central office codec that supports Full Rate and G.Lite asymmetric d igital subscriber line (ADSL) transmission is described. The transmit chann el consists of application-dependent digital filters, a 14-bit, 8.832-MSamp le/s current steering DAC, a 1.104-MHz analog filter, and a programmable at tenuator. Due to extensive on-chip digital signal processing, the codec com plies with the ADSL transmit power spectral density standards without exter nal filtering. The receive channel contains -17.5 to 33.5 dB of programmabl e gain staggered strategically across three stages, a 138-kHz analog low-pa ss filter, a 14-bit, 2.208-MSample/s pipeline ADC, and a digital 138-kHz lo w-pass filter. The receive channel has a wide input range that can accommod ate large line voltages present at the line hybrid circuit. The IC occupies 55.2 mm(2) and dissipates 450 mW from a 3.3-V supply.