An ultralow-power UHF transceiver integrated in a standard digital CMOS process: Architecture and receiver

A broad range of high-volume consumer applications require low-power batter y-operated wireless microsystems and sensors. These systems should concilia te a sufficient battery lifetime with reduced dimensions, low cost, and ver satility. Their design highlights the tradeoff between performance, lifetim e, cost, and power consumption. Also, special circuit and design techniques are needed to comply with the reduced supply voltage (down to 1 V, for sin gle battery cell operation). These considerations are illustrated by the design of a prototype receiver chip realized in a standard 0.5-mum digital CMOS process with 0.6-V thresho ld voltage. The chip is dedicated to a distributed sensors network and is b ased on a direct-conversion architecture. The circuit operates at 1-V power supply in the 434-MHz European ISM band and consumes only 1 mW in receive mode. It achieves a -95 dBm sensitivity for a data rate of 24 kb/s.