A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory-cell area efficiency of 33%

Authors
Yokoyama, Y Itoh, N Hasegawa, M Katayama, M Akasaki, H Kaneda, N Ueda, T Tanaka, Y Yamasaki, E Todokoro, M Toriyama, K Miki, H Yagyu, M Takashima, K Kobayashi, T Miyaoka, S Tamba, N
Citation
Y. Yokoyama et al., A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory-cell area efficiency of 33%, IEEE J SOLI, 36(3), 2001, pp. 503-509
Citations number
6
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE JOURNAL OF SOLID-STATE CIRCUITS
ISSN journal
00189200 → ACNP
Volume
36
Issue
3
Year of publication
2001
Pages
503 - 509
Database
ISI
SICI code
0018-9200(200103)36:3<503:A1E1DM>2.0.ZU;2-A
Abstract
A 1.8-V embedded 18-Mb DRAM macro with a 9-ns row-address-strobe access tim e and memory-cell area efficiency of 33% has been successfully developed wi th a single-side interface architecture, high-speed circuit design, and low -voltage design. In the high-speed circuit design, a multiword redundancy s cheme and Y-select merged sense scheme are developed to achieve the perform ance goal. In the low-voltage design, a dual-complement charge-pump scheme and a decoupling capacitor utilizing a tantalum-oxide capacitor are develop ed to retain high performance at low supply voltage.